The present invention relates semiconductor integrated circuit memories.
Development of dynamic random access memories (DRAMs) has concentrated on the one transistor cell ever since the breakthroughs incorporated in the generation of 16K DRAMs announced around 1970. With many incremental advances in technology, this technology has been scaled to the point where several one megabit DRAMs, all of them using single-transistor cells (and many of them using essentially the same single-transistor cell as was used in the 16K DRAMs) have recently been announced. As the memory technology has advanced, one of the necessary changes is that the cell size must be made smaller, so that an adequate number of memory cells can be fit into a feasible chip area.
However, this shrinkage in cell size, while intrinsically highly advantageous, has produced some significant problems with conventional technology. One of these problems is the sense amplifier pitch. That is, if one sense amplifier along the edge of an array of memory cells is connected to every two columns of memory cells, then the permissible spacing of the memory cells will be constrained by the possible width of the sense amplifiers, if the sense amplifiers cannot be made as narrow as twice the width of one column of minimum-geometry memory cells. Moreover, the ideal memory cell, would be, in effect, a crosspoint in a wiring matrix; by contrast, conventional memory cells are not located at every bitline and word line intersection in a memory array, but rather at every other bitline/word line intersection. However, if such an ideal cross-point DRAM cell becomes available, the problem of sense amplifier pitch will obviously immediately become much more acute. Recent inventions of common assignee have indicated the possibility of such a cross-point DRAM cell; see U.S. patent application Ser. Nos. 679,168 654,285, and 655,972, which are hereby incorporated by reference.
Another important problem of the prior art is bitline capacitance. This is becoming a more serious problem as technology seeks to advance beyond the one megabit level, for several reasons. First, simple scaling laws indicate that, if a 16K DRAM were simply scaled up, the number of memory cells per column would increase as the square root of the number of bits on the chip. However, a bitline connected to 512 memory cells would have a very large capacitance. Large bitline capacitances are undesirable for several reasons. One of them is that the bitline capacitance is typically substantially larger than the storage capacitance of the memory cell, so that the limited voltage swing available at the cell node is further reduced by at least the ratio of these capacitances. Thus, other factors being equal, larger bitline capacitance means that less noise immunity is available when the output of a memory cell is being sensed, and this advantage can alternatively be traded off for a number of other advantages. Moreover, reduced bitline capacitance also typically means higher speed in the column sensing operation, since lowering the capacitance of the bitline will also lower the RC time constant associated with it. A closely related problem is delays in the word line. In a large memory array, the word line (i.e. the line which addresses the single pass transistor of each cell in a row of cells in the prior art) will typically have an RC time constant which imposes a quite substantial fraction of the total delay required for accessing the cell. Thus, shortening the word line will lower its RC time constant by lowering both its resistance and capacitance, and therefore would be highly desirable.
These pressures have been dealt with in the prior art by increased segmentation of the memory cells into sub-arrays, but this approach also has its own difficulties. First, sub-array-select logic must be used at the chip level, which imposes additional delays and requires additional area. Second, if the number of sub-arrays is made very large, the wiring needed to interconnect the sub-arrays may itself begin to be a substantial demand on area and on processing.
Another factor which has put additional pressure on bitline capacitance and word line capacitance is a change in the nature of scaling at small geometries. That is, the capacitance per unit length of a metal line which is 10 microns wide will be approximately twice the capacitance per unit length of a metal line of equal thickness which is only five microns wide. However, at smaller geometries, the fringing fields of the corners of the patterned conductors become important, so that this scaling relation does not obtain any longer. That is, a metal line (or polysilicon, or silicide or polycide) which is 0.75 of a micron wide will have much more than half the capacitance of a similar line which is 1.5 microns wide, while its resistance will probably be doubled. This means that scaling laws which have operated favorably in scaling down to 1.5 microns cease to operate so favorably, and thus further scaling is made difficult.
To solve these two problems, the present invention provides a DRAM transistor cell which has two pass transistors connected in series. This additional transistor per cell provides the capability for multiplexing a sense amplifier among several columns, or of segmenting the word lines or the bitlines, without the additional levels which otherwise may be required for bitline segmentation.
In addition, the present invention teaches embodiments of a DRAM cell having two pass transistors which require no additional area over that required by a DRAM cell having one pass transistor. In particular, one particularly preferred embodiment of the present invention teaches a DRAM cell wherein the capacitor is formed in a trench, and the pass transistors are formed as thin polysilicon channel transistors within the trench. Thus, no additional horizontal area is taken up by the extra pass transistor.
A key point of the present invention is minimization of the parasitic capacitance of the node between the two pass transistors. This parasitic capacitance gives a mechanism for the storage charge to be pumped out of the memory cell. For example, if the transistor which is directly connected to the storage capacitor is turned on, charge sharing between the parasitic capacitance node and the storage capacitor will occur, and thereafter, when the other pass transistor turns on, charge can be shared between the parasitic capacitance and the bitline. Thus, charge has left the cell without the cell's ever having been fully selected, and this provides a leakage mode. Thus, the cell of the present invention is preferably constructed as a "charge-coupled" cell, i.e., the capacitance of the node between the two transistors is preferably minimized.
One main embodiment of the invention reduces this parasitic capacitance by using both frontside and backside gates to address a common polysilicon channel: the gates are offset, so that both must be turned on to connect the capacitor to the bit line, but they are also overlapping, so that charge pumping through the node between them is minimized.
Although the versions using a polysilicon-channel transistor are presently preferred, other embodiments of the present invention use a bulk (monocrystalline-channel) transistor. It should be noted that, in both transistor embodiments, a minimum-geometry patterned gate length can be used for both transistor gates, since there is no n+node between the transistors to provide outdiffusion. That is, the effective channel length of each of the two pass transistors is reduced by outdiffusion from only one side, so that the ratio of effective length to pattern length is higher than it would otherwise be. Moreover, this means that punchthrough is much less of a problem, even at very short patterned channel length.
Thus, the present invention provides a DRAM cell which provides greatly increased flexibility in design of DRAM arrays.
The present invention also provides DRAM arrays wherein column multiplexing is used to provide increased sense amplifier pitch.
The present invention further provides a cross-point DRAM cell array wherein sense amplifier pitch does not limit density.
To achieve these and other objects, the present invention provides: A dynamic random access memory cell comprising: a storage capacitor; first and second pass transistors connected in series to selectively connect said storage capacitor to a bitline.
The present invention also provides: A dynamic random access memory cell comprising: a storage capacitor; a pass transistor selectively connecting said storage capacitor to a bitline, said pass transistor having a channel region which is capacitatively coupled both to a frontside gate and to a backside gate, said frontside and backside gates each being conductive but not being connected together, said frontside and backside gates respectively being coupled to overlapping but laterally separate portions of said channel region.
The present invention also provides: A dynamic random access memory comprising: a plurality of memory cells arranged in rows and columns, ones of said memory cells comprising a storage capacitor and a first pass transistor comprising a gate connected to a wordline and a second pass transistor comprising a gate connected to a column select line, said first and second pass transistors being interposed in series between said storage capacitor and a bitline; and a plurality of sense amplifiers each connected to more than one pair of said bitlines and each comprising multiplexing transistors each controlled by one of said column select lines to selectively connect each said sense amplifier to no more than one of said pairs of bitlines.
The present invention also provides: A dynamic random access memory comprising: a plurality of memory cells arranged in rows and columns, ones of said memory cells comprising a storage capacitor; a pass transistor selectively connecting said storage capacitors to a bitline, said pass transistor having a channel region which is capacitatively coupled both to a front side gate and to a back side gate, said front side and back side gates each being conductive but not being connected together, said front side and back side gates respectively being coupled to overlapping but not completely coincident portions of said channel region, one of said two gates being connected to a wordline and the other of said two gates being connected to a column select line; and a plurality of sense amplifiers each connected to more than one pair of said bitlines and each comprising multiplexing transistors each controlled by one of said column select lines to selectively connect each said sense amplifier to no more than one of said pairs of bitlines.
According to the present invention there is also provided: A dynamic random access memory comprising: a plurality of memory cells arranged in rows and columns, ones of said memory cells comprising a storage capacitor and a first pass transistor comprising a gate connected to a segment select line and a second pass transistor comprising a gate connected to a wordline, said first and second pass transistors being interposed in series between said storage capacitor and a bitline; and a plurality of sense amplifiers, each connected to at least one pair of said bitlines.